1. Technical Field
The present invention is directed to post-silicon system-on-chip (SOC) operational validation. More specifically, the present invention is directed to an apparatus, system, computer program product and method of performing post-silicon validation with limited CPU use of a communications network.
2. Description of Related Art
An SOC is a semiconductor device (i.e., a chip) that includes all necessary hardware and electronic circuitries for a complete computer system. That is, an SOC may include on-chip memory, one or more microprocessors or CPUs (central processing units), peripheral interfaces, input/output (I/O) logic control, communications network, data converters etc. Generally, each group of hardware and electronic circuitries that performs a particular function in an SOC is referred to as a core. Thus, the CPUs, the I/O logic control, the data converters etc. may each be referred to as a core.
As with any semiconductor device, pre-silicon (i.e., before semiconductor fabrication) functional verification, and post-silicon (i.e., after semiconductor fabrication) operational validation are critical to the functional and operational quality of the device. This is especially true for an SOC device in which one defect may cause the failure of the entire device.
As is well known in the field, pre-silicon functional verification testing is time-consuming and is inherently un-encompassing (i.e., not every possible condition can be tested). Consequently, “bugs” may remain undetected in the SOC after pre-silicon functional verification testing has been performed. Note that the “bugs” may be due to misinterpretations of functional requirements as well as to incorrect assumptions during design. Further, bugs that are due to workmanship and materiel defects may be introduced during fabrication. Consequently, it is essential that exhaustive post-silicon functional validation tests be performed on an SOC. The tests should preferably include interactions by the cores as well as with other peripherals and subsystems.
One of the post-silicon functional validation tests that is rather important for an SOC is load stressing. In a load stressing test, the CPU or one of the CPUs (if there is a plurality of CPUs in the SOC) may coordinate execution of tests by the cores and validate the results of the tests. The tests may concurrently be executed by the cores. During the execution of the tests, the cores may interact with each other and thus may have to contend for the use of the communications network. Further, in coordinating the execution of the tests and validating the tests, the CPU may also contend for the use of the communications network as well as use the communications network. Having the CPU use the communications network when it is needed by the cores during the execution of the tests reduces the parallelism aspect of the tests. In addition, the desired test coverage of multi-core interaction and communications network contention may suffer.
Thus, what is needed is an apparatus, system, computer program product and a method of performing post-silicon validation with limited CPU use of a communications network.